1. Field of the Invention
This invention relates to OR.AND logic circuits Where field effect transistors (FETs) are employed as separate inputs to an OR gate and unidirectional current conducting means, such as a diodes, are employed as inputs to an AND gate.
2. Related Art
FIG. 1 shows a known basic digital inverter circuit 10 employing source coupled FET logic (SCFL). Therein, FETs 12 and 14 have their source regions coupled at 15. FETs 12 and 14 switch their on/off state when voltage V.sub.IN exceeds voltage V.sub.Rl. The on/off state of FETs 12 and 14 are always opposite one another. Thus, current flowing between ground and V.sub.ss is steered either through resistor 16 or 18, but never both. FETs 20 and 22 are buffers and the output is taken at either NOR or OR.
FIG. 2 shows an extension of the circuit of FIG. 1. Therein an R-S clocked flip-flop 24 is shown employing SCFL. In effect, the switching gate of circuit 10 (i.e., FET 12) is expanded in series into stacked FETs 26 and 28. Current will flow from ground through resistor 30 only if the SET voltage is higher than the voltage RESET and the CLOCK voltage is higher than voltage V.sub.R2.
FIG. 2 essentially expands the current source of FIG. 1 (i.e, R.sub.s and V.sub.ss in combination) in series by stacking FETs 26 and 28 in series. FETS 26 and 28 could be used to provide an AND logic function due to their series configuration. However, since the fan-in of the logic gate in FIGS. 1 and 2 is limited, in large part due to the current available to the gate, in order to perform logic operations on a number of inputs which is larger than the fan-in one would have to add additional FET AND gates or increase the available current. The first option greatly increases chip area and the latter, in addition to increasing power consumption, is often difficult to achieve since the voltage supply size is limited by chip design rules.
SCFL is an attractive logic family because it provides very fast switching. It is also nearly independent of the threshold voltage of the switching FET since the critical level of the transfer characteristics is equal to the externally applied reference voltage V.sub.R. SCFL is particularly useful when metal-semiconductor FETs (MESFETs) are employed with a GaAs substrate.
Therefore, it is highly desirable to have an OR-AND logic gate which can perform AND operations on a large number of inputs without stacking FETs as in FIG. 2 or without adding FET AND gates, while also maintaining the voltage supply at typical chip design levels.